This is an opportunity for a skilled IC Layout Engineer to join a dynamic team working on physical implementation and verification of mixed-signal and analog ASIC functions. Within this role, you will help to deliver state of the art IC within deep submicron CMOS technologies.

The responsibilities of the IC Layout Engineer include:

• Work on preparing layout reviews.
• Help with the full-custom physical implementation of high speed analog blocks.
• Help to optimise the layouts to meet performance requirements.
• Perform the sign-off for physical verification of sub-blocks.
• Help to write documentation in occurrence to the company's quality policy.

Additional requirements of the IC Layout Engineer will be:

• Solid understanding of Cadence.
• Able to work within a team and communicate effectively.
• Experience with mask design for analog or mixed signal functions.
• Prior participation of an IC product from specifications to mass products.

If this sounds of interest to you, contact Molly at IC Resources for more information.

Tel: +44 (0)118 907 3078